AnsweredAssumed Answered

AD9959 SPI Timing

Question asked by rbe on Jul 9, 2012
Latest reply on Apr 23, 2015 by


I have connected a AD9959 to an FPGA using a 3-wire SPI interface using 2 DDSs within a PLL.

Point 1 - 3 are executed once in the beginning, Point 4 is executed repetitivly for these 2 DDS every 16 us.


When starting the DDS communication I do the following steps:


1.   generate a MASTER_RESET (pulse width 1.7 us, time to next rising edge of SCLK: 3us)

2a. write the value 0xCF to reg. 0x00

2b. readback reg. 0x00

3a. write the value 0x940000 to reg. 0x03

3b. readback reg. 0x03


repeted access:

4a. set the channel enable in reg 0x00

4b. write the frequency to reg 0x04



The SCLK is generated only when needed for data transmission


Results and Question:


a) With SCLK = 11 MHZ everything works fine

b) Starting with SCLK = 11 MHz and then switching to SCLK = 33MHz still works fine .

     That means point 1 - 4 is first executet at SCLK = 11 MHZ and

      after changing SCLK frequency point 4 is executed at SCLK = 33 MHz



c) Seting SCLK = 33 MHz and executing then point 1 - 3 results in a failure.

More precise analysis shows that even the first register write (point 2) fails and

the value 0x00 is read back instead of 0xFC .


Why can I not initialise the DDS with 33 MHz?

My intention was to do all at 100 MHz. Is this possible or not?



The picture shows the signals generated by the FPGA for an access with SCLK = 11 MHz (Point 1,2,3 and one access of 4)


C2: /CS

C3: SDIO_0

C4: Master_Reset


Thanks for your help and kind regards