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AD9826 single SHA-Mode: clock generation+data output errors

Question asked by fullwell on Jul 6, 2012
Latest reply on Jul 11, 2012 by EBarnes

Hello there,

 

I'm using the AD9826 to sample pixel from a NIR-sensor. I have 48 pixel. I generate the CDSCLK2 and ADCCLK clocks with a FPGA.

 

Settings are: 1-channel-SHA, Blue-Channel, 4V Input Range, 4V Input Clamp Bias, 0V Offset, gain=1

 

I got 2 questions:

 

1) In the datasheet there is the info that the output data latency is 3 ADCCLK cycles.

 

My question is wether my generated clocks are correct:

 

Does it mean that:

a) pixel number no.1 is comming out of the AD9826 on the 4.rising edge of ADCCLK (MSB) and the 4.falling edge of ADCCLK (LSB)?

b) pixel no. 48 is comming out of the AD9826 with the 51. rising edge of ADCCLK (MSB) and the 51.falling edge (48+3 latency) of ADCCLK (LSB)?

 

Or does it mean that:

 

a)

a) pixel number no.1 is comming out of the AD9826 on the 4.rising edge of ADCCLK (MSB) and the 4.falling edge of ADCCLK (LSB)?

b) pixel no. 48 is comming out of the AD9826 with the 52. rising edge of ADCCLK (MSB) and the 52.falling edge (48+4 latency) of ADCCLK (LSB)?

 

2) To test the ADC i set a constant Voltage=3.3V at VINB. If I now set 3.34V at OFFSET-Pin normaly the ADC output should be ZERO. But I always have some bits floating (0-161counts). Strange thing is that this only happens on ADCCLK cycle number 4. At all other  samples the output is constant ZERO. What could be the reason of this?

 

Thanks for response!

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