RESET is used to synchronise LO dividers in multiple AD9279.
This is the procedure I follow to reset multiple AD9279.
1. Select multiple IC's and set mode to CW mode via SPI
2. Activate 4LO clock at 10MHz
3. On the second falling edge of 4LO assert RESET
4. On the next falling edge deassert RESET
5. Set phase and enable channels one by one.
Finally to leave CW mode
6. Select multiple IC's and set mode to chip run via SPI
7. Bring 4LO clock to low state.
On feeding a test signal to channels within an IC, they work as expected, but diffent IC's dont seem to work synchronously. i.e the RESET pin does not do its work. Stopping clock and redoing steps 1 to 5 make dividers come up in different phase states which is random. The datasheet says that LO dividers of multiple IC's come up in different states during power up, but I have noticed that stopping and restarting the the 4LO clock too make the dividers change phase.
The voltage levels, setup and hold timing of RESET is well within spec. I tried different combinations of steps 1 to 5 mentioned above, but without any success. Any help is appreciated.