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ADV7611 LLC output clock duty cycle in clock doubler mode

Question asked by qhall on Jul 3, 2012
Latest reply on Jul 11, 2012 by mattp

We have observed that the LLC clock output on the ADV7611, when operated in SDR mode (clock doubler bit IO Map Address 0x19[6] = 1), has a duty-cycle which varies from clock edge to clock edge in a repeating fashion.  The high time of the LLC signal varies on every sequential clock cycle, varying from 8.9ns during one cycle, to 7.3ns in the next as shown in the example traces attached.

 

We understand that the operation of a DLL-based doubler may incorporate multiple inverter based delay lines and that this might be the cause of this artifact, assuming that separate delay lines are used for generation of the doubled clock on the positive and negative edges of the source clock.

 

Can anyone confirm that the behaviour that we are seeing is normal, and also advise as to the cause?

 

- Quenton

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