Im using a custom board with AD9548 connected to an GPS retriever. I was able to successfully configure the device to get the 10Mhz output frequency locked to 1PPS signal(output from DDS at 80Mhz divided by 8). Now I wanted to generate 10Mhz clock phase alignment to PPS and Im a bit confused about phase alignment mechanisms in AD9548 described in datasheet.
As I understand the phase alignment is done by a clock distribution synchronization. When I configured active reference synchronization to frequency or phase lock I see on the oscilloscope that the output clock of AD9548 is only phase aligned for some time after the lock event. But when I select the DPLL feedback edge as a synchronization source the output clock signal seems to be phase alignment all the time with PPS.
Can you advise how should I configure the device and what are the differences/use cases for the two sync modes?