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ADV7441A CVBS to 24 BIT RGB TIMING ISSUE

Question asked by daoyin Employee on Jun 27, 2012
Latest reply on Jun 28, 2012 by GuenterL

One of our customer use ADV7441A to receive CVBS and HDMI signal, outout is RGB444 24bit

For CVBS input, the signal chain is:

CVBS-->ADV7441A (SDP)--->TTL(Discrete Hsync,Vsync,DE)--->SiI9134

When HDMI pretest, we find it can not match CEA861 480i standard,especially vertical pulse delay(Front porch, for example field0, it should be 4 lines, but test result is 4.88 lines) and Vertical pulse width (it should be 3 lines, but the test result is 6 lines and 270 pixels)

I try to adjust the setting with User map 0X34,0X35,0X36, the vertical pulse delay can be changed,but the Vsync width can not be modified when SDP process.

I think if I use SiI9134 internal DE generator, it can only changed the Delay ( H, V front/back porch),but can not change to width.

For HDMI 480i input to ADV7441A, the output timing can be modified to match CEA861.

 

If there are any method I missed?

Any suggestion is welcome

 

The CVBS setting as below:   ADV7441A_ADV7441A@_ADV7441AVDP_ADV7441AHDMI_ADV7341-VER.MB3.0.TXT

 

##SDP CVBS##

:AUTODETECT CVBS (NTSC) 24 Bit 444  Out through HDMI TX:

42 00 0E ; CVBS INPUT ON Ain6

42 03 15 ; 24 bit 444 out, AV Code DUP

42 3C AD ; Setup SOG Sync level for divided down SOG

42 1D 40 ; Disable TRI_LLC.

42 31 18 ; New AV Mode

42 32 81 ; V Sync position control

42 33 84 ; V Sync position control

42 34 00 ; H Sync position control

42 35 22 ; H Sync position control

42 36 9E ; H Sync position control

42 3A 07 ; Power down ADC 1 & ADC2 & ADC3

42 3C A8 ; SOG Sync level for atenuated sync, PLL Qpump to default

42 37 A1 ; Hsync & Vsync out Positive Polarity 

42 47 0A ; Enable Automatic PLL_Qpump and VCO Range

42 E5 27 ; V Sync position control

42 E6 4F ; V Sync position control

42 F3 0F ; Enable Anti-Alias Filters

 

Tommy Chen

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