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AD9789  mixed mode (cmos-lvds) retiming

Question asked by amc on Jun 28, 2012
Latest reply on Jul 31, 2012 by danf

We are working with AD9789  using CMOS interface for data signals and LVDS for the sync signals (DCO and FS).

Do you have any available info about the retiming registers configuration in this mode?

 

The datasheet stands:

 

".....they can also be set to the following recommended safe values:

• In LVDS mode, DSCPHZ = 0, SNCPHZ = 3, LTNCY = 0 (see the Latency Register section)

• In CMOS mode, DSCPHZ = 0, SNCPHZ = 7, LTNCY = 0(see the Latency Register section) "

 

But since we are using a mixed mode which ones should we take? And BTW whats is the

meaning of "safe" in that extract of the datasheet

 

Thanks...

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