AnsweredAssumed Answered

SPI0 ISR Status Flag wrong - BF548

Question asked by Johan@Hannes on Jun 27, 2012

Hi @ all,

 

I run into an issue -a pretty strange behavoir- but let me summarize:

 

I try to start a simple interrupt driven SPI communication(RDBR - driven).Please find my code below.

I've written an interrupt routine and in my opinion I've initilized interrupt controller and registers properly.

Trying to read some byte(in SPI_CORE_READ( )) i tryied to initiate transfer by loading a command into TDBR Reg of SPI0 and afterwards making a dummy read. Now one could expect, that in SIC_ISR0 proper bit is set to signal interrupt and the program run into service routine. A Flag is set indeed, not for SPI0 status interrupt but for SPI0 DMA4 channel. Further i don't get to ISR at all. What I'm doing wrong?

 

Thanks for help in advance!

 

#define EBIU_DDRCTL0_DEF       (UINT32)(0x220A840DU)   /* PRQA S 303*/ /* AD definition, DDR CTL 0*/
#define EBIU_DDRCTL1_DEF       (UINT32)(0x10026222U)   /* PRQA S 303*/ /*AD definition,  DDR CTL 1*/
#define EBIU_DDRCTL2_DEF       (UINT32)(0x00000061U)   /* PRQA S 303*/ /* AD definition, DDR CTL 2*/
#define VRCTL                  (UINT16)(0x40DB)       /* PRQA S 303*/ /* AD definition, VRCTL*/

 

#define CORE_SPI_CONFIG_RD(MSTR|POLARITY_HI|CLKPHA_LO|RDBR_CORE)

 

 

VOID InitCommon()

{

   CPU_Init();      

   SPI_INIT();

   (VOID)register_handler(ik_ivg7, (SPI0_TX_ISR));       //Register the SPI0 interrupt handler

   *pSIC_IAR0   &= ~(0x00200000);                        //Interrupt Assignement Reg. SPI0 Status

   ssync();

}

 

VOID CPU_Init (VOID)

{

  ADI_SYSCTRL_VALUES tSysCtrl; 

 

  // program the PLL for a 400MHz Core CLK, and 100MHz SCLK

 

  //(based on CCLK = CLKIN*MSEL; SCLK = CCLK/SSEL; here: MSEL = 16, SSEL = 3 and CLKIN = 25MHz)

 

  tSysCtrl.uwPllCtl = PLL_MSEL_VALUE<<9;

 

  tSysCtrl.uwPllDiv = PLL_SSEL_VALUE;

 

  tSysCtrl.uwVrCtl  = VRCTL;

 

  //response will not be handled, since not necessary

  (void)bfrom_SysControl( SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_PLLDIV  | SYSCTRL_VRCTL | SYSCTRL_INTVOLTAGE, &tSysCtrl, NULL);

    ssync();

 

  // configure the EBIU based on calculation from 'Firmware/Doc/BlackfinRegisterCalculations.xls'

  *pEBIU_DDRCTL0 = EBIU_DDRCTL0_DEF;                       /* PRQA S 303,1281*/ /* AD definition*/

  *pEBIU_DDRCTL1 = EBIU_DDRCTL1_DEF;                       /* PRQA S 303,1281*/ /* AD definition*/

  *pEBIU_DDRCTL2 = EBIU_DDRCTL2_DEF;                      /* PRQA S 303,1281*/ /* AD definition*/

  

  ssync();

}/*CPU_Init*/

 

VOID SPI_INIT()

{

 

   DISSpi0();

 

   *pPORTE_FER      |= PE0 | PE1 | PE2;                         //FER Reg.Port E

   *pPORTE_MUX      |= MUX0_0 | MUX1_0 | MUX2_0;        //MUX-->enable SPI channels

   *pPORTE_DIR_SET  |= (PE4);                                       //Config. CS for SPI0

   *pSPI0_BAUD       = BAUD_RATE_DIVISOR;                 //Set Baud rate

      ClearCS();                                                                 //Pull up CS 

   ssync();

}

 

VOID SPI_CORE_READ(UINT32 u32Count, UINT32 u32Address)

{

 

   BYTE bDummyread = 0x00;                                                          /* PRQA S 3203*/ /* Variable needed to empty RDBR*/

   UINT16 u16I;

   u32ReadBufferCount=u32Count;                       //Bytes to read

 

 

    DISSpi0();                                                                //Disable SPI0

    *pSIC_IMASK0 |= 0x00000020;                                  //Interrupt Mask Reg., Enable Interrupt SPIO Status

    ssync();       

    *pSPI0_CTL    = CORE_SPI_CONFIG_RD;                 //Config. SPI0_CTL Reg.      

   ssync();       

   ENSpi0();                                          //Enable SPI0 

 

   TriggerCS();                                       //Trigger CS   

 

    *pSPI0_TDBR = CC2400_READ_COMMAND|u32Address;      /* Send read command + Address */

   bDummyread = (BYTE)*pSPI0_RDBR;                                   /* Dummy read to empty RDBR and trigger read operation */

 

}

 

EX_INTERRUPT_HANDLER(SPI0_TX_ISR)

{   

   *pSPI0_TDBR = u16Dummy;                               //Dummy write

   aui8BufferR[u32BytesRead]=*pSPI0_RDBR;         //Read receive buffer

   ssync();

  

}

Outcomes