I am using AD56668 -2 ABRUZ DAC ic in our new design.
But i am facing problem in programming. I have generated SCLK with 50Mhz frequency continuously.
Below all the clk cycles are reffered with respect to 50Mhz clock.
Initially all the control signals are driven as high from the FPGA.
Inititally CLR line is made low for 1 clk cycle. THis will execute only one time.
Update 32 bit shift register with data (X"ABCD",X"ABCD",X"ABCD"), Command ("0000") ,Add ("1111").In 3 loops also i am sending the same data.
SYNC line made low for one cycle.
Data is shifted 32 times from the data register.
then LDAC made low for one clock cycle.
But the output of DAC is '0'. I am not able to see any voltage on the output.
Can you please suggest me some ideas / if any thing wrong in the procedure also can you please tell me?