We have a setup that connects the TI Davinci chip (6467T) with the adv7441a chip as it's HDMI video input. We've seen the problem "Video Out Of Sync" described in the attached TI document (section 2.1, page 2). In the document TI states that the enabling of the VPIF is to be done only after VSYNC and HSYNC are marked as valid. From various reasons we cannot follow that guide line and instead we enable the VPIF after:
reading register UserMap1 HDMI_RAW_STATUS_3 (0x68 bits 0x3) - TMDS PLL is locked and HDMI is being received),
reading register HDMI Map REGISTER_04H (0x04 bits 0xa) - TMDS clock detected and TMDS PLL clock locked) and if all bits are set than we have a valid HDMI input and we turn VPIF on.
My questions are:
- Is the HDMI output of the 7441a chip always valid when the bits are set ?
- Can we assume that the bits will be set only after the HSYNC and VSYNC are valid ?
Assuming the answers to both questions are yes can you explain the HDMI flow that causes the 7441a to raise the HSYNC/VSYNC lines and what follows after that and sets the bits we're looking for.