In ADV7181C_Manual_RevB. PDF datasheet, how to calcuated the values PLL_DIV_RATIO[11:0] and FR_LL [10:0] which are corresponding to the registers 0X87, 0X88, 0X8F and 0X90?
PLL_DIV_RATIO for standard resolutions are specified in Table 10 & 11. Basically the PLL divisor is the samples per total line times the oversampling rate.
The charge pump current selection is defined in paragraph 7.3.5.
FF_LL is the count to 28.63636 MHz clocks for one line. If zero then it uses a value derived from PRIM_MODE. Check out paragraph 9.5 of the manual.
Retrieving data ...