1. May I know whether ADAU1701 can support for PLL slave mode ?
As I know that in different MCLK input need to be catered for different audio sampling rate during PLL master mode.
Our design need to support for 48KHz,44.1KHz,16KHz and 8KHZ audio sampling rate, then MCLK input have to be changed
accordingly when audio sampling rate change. The problem is our design cannot cater for so many different MCLK.
If ADAU1701 can take BCLK as reference clock during PLL slave mode then we don't need MCLK anymore.kindly refer to diagram below
2. some other supplier support master mode, without change MCLK, internal PLL can support different sampling frequency, can ADAU1701 do that as well, if not, what the recommendation to implement this requirement.