AnsweredAssumed Answered

AD9889B - Are my register settings OK? No TMDS Data!

Question asked by Billabonguk2003 on Jun 18, 2012
Latest reply on Jun 22, 2012 by DaveD

Please could somebody take a look at my reg settings and schematic.  I am attempting to input BT.656 576i video from an FPGA (Multiplexed 10 bit YCbCr with embedded syncs Note - FPGA has all lines connected so could potentially change video output style) and output in HDMI format RGB 4:4:4

 

I have read the programming quick start guide and the other posts in the forum and have tried  implementing the suggestions made. 

 

Here are my reg settings:

 

W 72 41 10 / Power up

W 72 A1 7C / Power down TMDS

W 72 AF 06 / Disable HDCP, disable HDCP encryption, set HDMI mode

W 72 01 00 /      |

W 72 02 18 /      |

W 72 03 80 /      |      CTS=3000, N=6272

W 72 07 00 /      |

W 72 08 75 /      |

W 72 09 30 /      |

W 72 0A 0D / CTS auto, audio I2S, MCLK SPDIF inactive, MCLK I2S active, MCLK 256xfs

W 72 15 28 / 48KHz audio sampling, 10bit YCbCr 4:2:2 2xPxl Clk, refresh above 30Hz

W 72 16 14 / Output RGB 4:4:4, input 10bit 4:2:2, input style 2, DDR input edge falling

W 72 17 04 / VSync & HSync pol high, clr space +/-1, -4096 to 4095, 1st order 4:4:4 upconv, ratio4:3, DE gen dsbl

W 72 30 03 /      |

W 72 31 03 /      |      HSync placement=12, HSync duration=63

W 72 32 F0 /      |

W 72 33 08 /      |      VSync placement=2, VSync duration=3

W 72 34 03 /      |

W 72 35 20 /      |      HSync delay=131

W 72 36 D6 /      |      VSync delay=22

W 72 37 05 /      |      Interlace offset=0

W 72 38 A0 /      |      Active Width=720

W 72 39 12 /      |      Active Height=288

W 72 3A 00 /      |

W 72 44 00 / dsblSPDIF , dsblN_CTSPkt, dsblAudioSamplePkt, dsblAVIInfoPkt, dsblAudInfoFrame, dsblSparePkt

W 72 45 00 / Clear AV Mute, Output format RGB, no format information data, no bar information

W 72 46 04 / No scan info data, no colorimetry data, picture aspect 4:3, no non-uniform picture scaling

W 72 47 80 / Active format same as aspect ratio

W 72 BA 60 / No video Clk delay

W 72 96 C0 / HPD Interrupt & Rx Sense Interrupt active

W 72 98 07 / RSVD MUST WRITE

W 72 9C 38 / RSVD MUST WRITE

W 72 9D 61 / RSVD MUST WRITE

W 72 A2 87 / RSVD MUST WRITE

W 72 A3 87 / RSVD MUST WRITE

W 72 BB FF / RSVD MUST WRITE

/W 72 A5 C0 / Data sheet says default [0x4] but forum says 0xC0

/W 72 AB 00 / Data sheet says default [0x40] but forum says 0x00

W 72 A1 00 / Power up TDMS

 

I believe that video is being input correctly as I can read back PLL lock and VIC correctly. 

 

Register values read back:

 

0x00      00 00 18 80 01 28 15 00 75 30 0D 0E 3C 18 01 13

0x10      25 37 00 00 00 28 14 04 06 62 04 A8 00 00 1C 84

0x20      1C BF 04 A8 1E 70 02 1E 00 00 04 A8 08 12 1B AC

0x30      03 03 F0 08 03 20 D6 05 A0 12 00 80 00 55 00 C0*

0x40      00 10 E0 7E 00 00 04 80 00 00 00 00 00 00 00 00

0x50      00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0x60      00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0x70      00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0x80      00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0x90      00 00 00 00 CC 80 F4 00 07 02 00 18 38 61 10 00

0xA0      00 00 87 87 08 C0 00 00 00 00 00 00 00 00 40 06

0xB0      05 81 10 D9 35 36 49 7C B0 00 60 FF 00 00 00 00

0xC0      00 00 00 00 00 10 14 00 02 03 00 01 02 00 00 70

0xD0      70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70

0xE0      70 70 70 70 70 70 70 70 70 70 70 70 70 70 70 70

0xF0      70 70 70 70 70 70 70 70 70 70 7D AA 1C 00 B0

 

*reg 3f = C0 = 576i Active

 

Many thanks in advance for your help

 

Rob

Attachments

Outcomes