I am designing clock circuit using the AD9517-3.
I have two questions about CLK INPUTS.
Pls refer to P.6 Table3.
1.Data sheet describes "Input Level differential is 2Vp-p(Max).
Pls teach me the maximam input level of case of Single-Ended.
2.Also, "Larger voltage swings may turn on the protection diodes and may degrade jitter performance".
I think that it means Larger voltage swings may degrade jitter performance.
Could you explain me more detail?.
I'd like to know relation between input-level and jitter.
It would be greatly appreciated if advice could be gotten.