I'm using an ADV7180 video decoder to digitize an incoming PAL 625/50Hz signal. I'm using a custom board where the ADV7180 Pixel data port is connected to a DM642 videoport. The videoport will acquire the BT656 data stream and do further processing.
I must use the HSYNC signal provided by the ADV7180 as a "Capture enable" signal for the video port and so I must configure his shape and duration as specified by the DSP.
I'm experiencing something weird. If I leave registers 0x34, 0x 35, 0x36 with their defaullt values, the hsync pulse has his rising edge in the middle of the active luminance video signal (about..).
I'have an ADV212 P160 evaluation board, provided with an ADV7189 encoder, and i noticed that the behaviour is the same. In this case the ADV7189 is directly connected to the ADV212 compressor, and it all seems to work fine.
I'm using the followings values for the ADV7180 registers (in the form of ADDR - VALUE):
0x04 - 0xDC
0x17 - 0x41
0x31 - 0x02
0x34 - 0x00
0x35 - 0x02
0x36 - 0x00
0x3D - 0xA2
0x3E - 0x6A
0x3F - 0xA0
0x0E - 0x20
0x55 - 0x81
0x0E - 0x00
There is something wrong in this behaviour? ..i would expect the hsynch pulse to start whithin the analog sync pulse, not in the middle of the line.