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AD9859 PLL not locking on 100MHz reference clock

Question asked by Sparty on Jun 15, 2012
Latest reply on Jun 18, 2012 by Sparty

I'm trying to use the AD9859 in an application where I'd like a high frequency external clock (100MHz) and use the on-board PLL multiplier at 4x to get to a SYSCLK of 400MHz.  My device doesn't seem to achieve phase lock with this combination as the frequencies of the DAC output signals are about 95% (independent of frequency) of what they should be (and not very stable) (SYNC_CLK frequency measures 94.8MHz).  With the PLL inactive and the external clock at 100MHz, the output signal frequency is stable and exactly what it should be.  Other combinations that generate a high SYSCLK frequency seem to work fine (e.g., 30MHz external and 12x multiplier = 360MHz SYSCLK).  The loop filter is 1k Ohm and 0.1uF as recommended in the data sheet.  I'd really appreciate it if someone can shed some light on this.  The high input clock frequency is important to me as I'm trying to keep the spectrum of interest free of local noise in a spectrum analyzer application.  Thank you much.