I'm trying to set CCLK and SCLK to its minimum value. But the emulator hangs when I run the code. What should I do?
1. Ensure that VCO is set to min of 50MHz. Look at the processor data sheet.
2. Ensure that the relationship between the JTAG and the core clock of the processor is maintained appropriately when JTAG is connected to your board. Typically, the core clock runs at the frequency that is more than 2x the JTAG clock’s frequency. If the core/JTAG clock relation is not followed, scan failures may prevent the emulator from connecting to the processor.
I have a BF537 EZ-Kit Lite and I'm interested in determining the minimum possible frequency that the core clock (cclk) can be set to (in full on mode). There is a lot of information (in the Analog literature) about the maximum achievable frequencies... but nothing on the minimum frequency, which is important to know if you're trying to drive down power costs.
The datasheet says that the minimum VCO frequency is 50MHz. I've been experimenting in C with the adi_pwr_SetFreq() function, but the minimum core clock frequency that I can achieve is 50MHz. I expected that the adi_pwr_SetFreq() function would set DF to 1 in the PLL_CTL register, and CSEL to 11 in the PLL_DIV register, which would give a minimum cclk frequency of 3.125 MHz ( = (VCO/2)/8 ).
Secondly, in Active mode, the core clock frequency becomes equal to 25MHz, i.e. the frequency of the crystal on the EZ-Kit. However, debugging then becomes difficult using the USB Debug Agent. So I have a second question- what is the minimum core frequency required to ensure that the Debug Agent (on the BF537 EZ-Kit ) will operate correctly?
Regards and thanks,
Those divides on the PLL registers should work fine. Your problem may be with the USB debug agent. I am not sure what the lowest allowable core / sys clk is that allows operation of the debug agent (someone else may need to jump on here to answer that) but you are likely running too slow.
However, you can test this low clock rate; you could try making a simple blink program on the ez-kit, load the program into flash memory, disconnect the usb debug agent, and check for functionality. Also, you should be able to verify the system clock by probing with a scope on the ez-kit on the clkout pin.
Hope this helps,
Your observation was right. If you look into the power service file
adi_pwr.c, close to the end of the function adi_pwr_SetFreq ( ), you'll find
the following line
adi_pwr_SetPLL(msel, df, ADI_PWR_CSEL_1, ssel, vlev);
From there, you can see, the CSEL is always set to 1, which means the core
clock is going to equal to the VCO clock all the time, regardless of your
settings of the CSEL bits. You have to make some changes here if you want to
achieve lower core clock frequencies.
Hope this helps.
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