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adv7393 embedded hsynch and vsynch with non-standard line length

Question asked by stephenh@gdls.com on Jun 13, 2012
Latest reply on Jun 15, 2012 by DaveD

We ran into this problem when trying to generate a 525i 16:9 video format (854x480) with the ADV7393.  

The overall timing is the same as standard SD 525i, but with a higher dot clock to get more "pixel" analog transitions in the active window..

The clock ends up being approximately 32MHz (about 18% faster).

 

We can input any of the combinations of SDR input data (bit width, color space, sync formats), so we've run through many of the SD configuration scripts (NTSC, PAL, square pixel, etc).

For the sake of discussion, assume we're running Script 66 from Analog Device's datasheet.

We're focusing on just the Luma (Y) output, so the color-burst timing is a non-issue for us and we don't care about its shift as we dial up the clock to hit the wider frequency.

At the higher clock rate, the Hsync pulse will end up being skinnied up a bit as well, but that's acceptable and I think there are some register settings to tweak that a little

 

At the 854 active pixel count, we end up around 1030 pixels total line length with the blanking and sync in there.

Normal pixel counts would be 720(ish) active with 138(ish) blanking for a total of 858(ish)

 

Here's a quick diagram of what the signal should look like with a standard test pattern (Y only, no chroma).  

It should be a standard RS-170 signal (albeit with possibly skinnier sync pulses).

 

However, this is what we actually get -- a spurious premature sync pulse followed by our triggered one:

 

From measuring the timing of that spurious sync, it appears to occur at about 860 pixels.  (Aha... 720 + 138 = 858 for NTSC...)

 

When we change to square pixel modes or PAL, this trigger point shifts, so the internal counter gets configured to different trigger points.

It moves left for NTSC square pixel (640 active), and moves to the left for PAL square pixel mode (768 active).

 

in SD Mode Register 5  (0x86), bit 6 controls that internal line counter, with a footnote attached to it:

 

So  with that bit set to 1, the counter will not trigger sync pulses anymore and they'll only occur when we input external syncs...

 

 

 

...OK, technically I guess that's what we get, but the footnote forgot to include "...and will completely crush the video output until such an external sync is applied."

Here is what we see:

The video output flatlines at that 860ish count point until an external sync is sent.   The level of this flatline is below that Blank level, but slightly above the sync tip level.

 

 

 

We have tried some things with the HD modes, and we can get the horizontal sync TIMING correct without the extraneous syncs (or flatlined output), but haven't sorted through all the various standards to see which might give us some sync pulse formats which would be compatible with the SD sync patterns.

 

 

 

So here are our questions:

1)  Are we missing something that makes the counter truly free running (or decouples it from the flatlined output feature)?

2)  if "flatlined video" is indeed a feature of this part, then is there a way to extend that counter interval out beyond the mode presets?    If so, how far out can that counter be set?

3)  Is there an ED or HD mode or configuration of registers which will give us 525i compatible syncs? 

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