AnsweredAssumed Answered

Why AD9889B PLL NOT locked

Question asked by kev on Jun 13, 2012
Latest reply on Jun 14, 2012 by DaveD

Try to use AD9889B as DVI output.

Digital input: Input ID =6 DDR with separate SYNC, Style 2, 8 bit YCbCr.

When input is XGA@60Hz, DVI output quality is perfect.

When input is SXGA@60Hz, DVI output has pixel noise on display monitor. But still see the picture constantly.

When input is UXGA 1600*1200@60Hz, DVI has no output at all. measure by scope, NO DVI output clock. Reading register 0x9E[4], indicate PLL NOT locked. Measure by scope, input DDR CLK, HSYNC , VSYNC, DE, DATA[7:0] are high quality.


1. Does AD9889B PLL solely use VIDEO CLOCK Input as reference clock? HSYNC and VSYNC have no effect on PLL?

2. Does AD9889B PLL use "delay cell" to adjust the Input Video CLK Capture? As register 0xBA states.

3. Where is the AD9889B PLL low-pass filter?

4. Your idea, why is PLL NOT locked? My input CLK is clean 162MHz for UXGA 1600*1200@60Hz.