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BF561 SDRAM interface

Question asked by HEGDE on May 15, 2009
Latest reply on May 15, 2009 by HEGDE

I am using ADSP-BF561 EZ-Kit. I have query of SDRAM interface with
BF-561 processor. MT48LC16M16A2 - 4 Meg x 16 x 4 banks

why BF-561 A18-A19 pin connected to BA0-BA1?

For example, if I am writing data to 0x1000000 SDRAM address, then it
goes to first bank means IA25-24 is 0x01 but what about A18-19?

Can you please explain me this in detail?