in the datasheet of AD9548 there is note that minimum DAC output frequency is 62.5Mhz. We programed the AD9548 DPLL to frequencies lower than that(eg. 10Mhz) and taken a look at driver output with osciloscope - it looked fine. The evaluation software also allows to program the output freqencies to lower than 62.5Mhz. Is there a special reason to not program the DDS to frequencies lower than 62.5Mhz?
Based on the facts from datasheet to generate 10Mhz output clock we should for example generate 80Mhz clock at DAC and then divide it down by 8? Or there is an better way to that? For example set the FTW directly to 10Mhz?