we have developed an custom board with AD9548 device. It looks like we are able to correctly configure the DPLL for synchronization with reference frequencies down to 10Hz. However when we want to use an 1PPS signal with the loop filter settings taken from app note AN-1079 (bottom of page 8 - loop BW = 0.02 Hz,phase margin = 60°,attenuation offset = 1 Hz,attenuation = 15 dB) the DPLL gets stuck at around 100kHz from programmed output frequency(we measure the output) and doesn't get locked. If we wider the BW of loop filter to 0.05Hz then the DPLL locks to desired freqency. If we narrow the loop BW to 0.01Hz the DPLL stops even further from desired frequency.
Is this a known issue? We thought the narrowing the loop BW only makes the lock process take longer but doesn't completely stop the process .Can you please help us to sort this problem out?
The DDS output frequency is set to 62.5Mhz The 1PPS signal was generated by a GPS retriever and by a signal generator. The system clock for AD9548 is generated by an high stability OCXO (5ppb). We also tried to generate the 1PPS and system clock from two channel signal generator - the problem still appears.