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about the PLL fractional mode in ADAU1361

Question asked by cheer2012 on Jun 4, 2012
Latest reply on Jul 25, 2012 by BrettG

Hi,guys,

    I'm now using ADAU1361 eval board , and SigmaStudio 3.6. And I found that if PLL fractional mode is used, and that fractional part value is too small(i.e. 0.0001), the PLL could not lock. See attached the picture. The oscillator on eval board is 12.288MHz, and I set VCO output to 49.153MHz purposely (actually it should be 48K*1024=49.152MHz),then PLL falls into unlock.

   I could not find any restriction about PLL fractional mode. And could you give some suggestion about this?

 

Thank you.

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