We are using the ADV7393BCPZ video encoder for a product that requires a wide aspect ratio analog video with the same timing parameters as standard 525i monochrome RS-170 (essentially just cramming more pixels per line at a higher pixel clock).
We are encountering a problem that the ADV7393 automatically generates a hsynch pulse after approximately 858 pixels on a line.
When we set register 0x86 to allow the counters to be free-running rather than resetting, the hsynch pulses go away, but the video signal from 858 pixesl out to our next generated synch pulse is flat-lined at 250mV and does not display any of the pixel data we send during that period.
It appears that even when the line/row counters are configured to be free-running, they still prevent video output after they hit some internal limit. That internal limit is quite clearly not a fixed limit as it changes for the square pixel and PAL configurations.
Going to the PAL Square Pixel settings, still gives us the double hsynch, though the active pixels before the generated hsynch is about 950 pixels. This is closer to what we want, but still not acceptable.
Using the HD (1035i/1080i) settings appears to limit us to the particular synch pulse waveforms for the specific video standards for HD, whereas we need the SD synch pulses.
We would like to set the counter limit within the ADV7393BCPZ to some value greater than 1000 so that it is NOT truncating the video signal!!!!! but nowhere in your documentation for the ADV7393BCPZ do you tell us the address of this counter or how to set it's count limit.