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TS201S SDRAM Controller - Bank Selection

Question asked by cib@alst on May 29, 2012
Latest reply on May 29, 2012 by RChary



Could someone explain how the TS201S SDRAM controller determines the number of rows per bank?

I need to interface a 1M x 32 x 4 banks SDRAM device (Micron MT48LC4M32B2B5) to a TigerSHARC and I'm not sure which address pins to connect to the SDRAM's bank select pins.


According to EE-201, any address line pair in the range A[11:15] can be used for for bank selection as long as they are not driven as part of a row or column address. I'm using A[11:0] for row/column addressing, so does it mean that I could use any of the following address pins pairs (EE-201 table 6) to drive the SDRAM's bank select pins:


1) A[13] & A[12]

2) A[13] & A[14]

3) A[15] & A[12]

4) A[15] & A[14]


I can see that the SDRAM controller wouldn't need to know the number of rows per bank, if the A[13] & A[12] drove the bank select pins as A[13:12] will automatically increment after the last row in a bank. If the other three options above are equally valid, then surely the controller must have a way of determining when it has reached the end of a bank. Is there something I'm missing?


Any help would be greatly appreciated