Could someone explain how the TS201S SDRAM controller determines the number of rows per bank?
I need to interface a 1M x 32 x 4 banks SDRAM device (Micron MT48LC4M32B2B5) to a TigerSHARC and I'm not sure which address pins to connect to the SDRAM's bank select pins.
According to EE-201, any address line pair in the range A[11:15] can be used for for bank selection as long as they are not driven as part of a row or column address. I'm using A[11:0] for row/column addressing, so does it mean that I could use any of the following address pins pairs (EE-201 table 6) to drive the SDRAM's bank select pins:
1) A & A
2) A & A
3) A & A
4) A & A
I can see that the SDRAM controller wouldn't need to know the number of rows per bank, if the A & A drove the bank select pins as A[13:12] will automatically increment after the last row in a bank. If the other three options above are equally valid, then surely the controller must have a way of determining when it has reached the end of a bank. Is there something I'm missing?
Any help would be greatly appreciated