Dear Analog Devices,
I'm working on an AD9910 setup that uses a highly stable reference clock of 10MHz which should be internally multiplied via PLL to achieve a system-clock-frequency as high as possible (ideally 1GHz) while keeping the phase noise on the DDS-output as low as possible.
My Problemis the following:
I used the Excel PLL-tool worksheet to derive some values for the loop-filter components (R1, C1, C2) but no matter which values I use (small loop bandwidth, high bandwidth, low Icp, high Icp) I always get a pretty bad phase noise plot for a DDS-output-frequency of f=100MHz which also looks very similar all the time (see attached image). I don't think that the problem is based on the Reference Oscillator since this one has a very good phase noise behaviour. I guess that my problem is based on the PLL-loop-filter as I suspect it to be the most critical when using the PLL.
The next thing I've tried was to recreate the phase noise plots shown in the AD9910 datasheet (Figure 16, p. 15, 1GHz operation with 50MHz reference and 20x PLL multiplier). I chose some PLL-loop-filter-component-values based on the worksheet, dialed in an output frequency of f=100MHz and din't even come close to the values presented in Fig. 16 (much worse, the phase noise plot looked similar to the one I've attached)
My questions now are:
- what were the exact DDS-settings for the datasheet measurement? (Charge pump current, ...)
- how was the PLL-loop-filter configured? (Values for R1, C1, C2).
Thanks a lot in advance for any answers or suggestions !!
- I already checked for a very clean power supply => O.K.
- the input level of the reference clock (10MHz) is also O.K. (~8dBm, works fine with all of my DDS-setups)
- I use the Rohde & Schwarz FSUP50 for phase noise analysis