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AD2S1205 12-Bit RDC Timing Problem

Question asked by Plex on May 29, 2012
Latest reply on Jun 6, 2012 by ShaneO

Hi everyone,


I have a timing problem with the AD2S1205 Resolver to Digital Converter.


But first my setting:

     I am using a Cyclone 3 FPGA

     The AD2S1205 is on a PCB, the schematic is nearly the same as on this Eval-board (I am not using this eval board).

     I program in VHDL and use Quartus2 for programming the chip


So here comes my problem:

I have connected all the ports in Quartus2 and loaded the finished program on the FPGA. On SignalTap I can see the outputs:


Fig. 1: Resolver SPI timing

In the datasheet it says: "the MSB is clocked out by the falling edge of nRD". In my case, the MSB is clocked out at the first rising edge of SCK (while nRD is low).

Then there is another sentence: "each subsequent bit of the data-word is shifted out on the rising edge of SCK". My subsequent bits are shifted out short after the falling edge.


I have looked at all the timings, they should be ok.


Does anyone have an idea why this happens?

I will read in 17 bits now on every falling edge and delete the first bit. This should do the trick. But I would like to know the reason why it is happening.


Greeting from Germany