we use ADSP-21489 and SPI flash in master booting mode. We designed our board with the same SPI flash M25P16 as on the ADSP-21489 eval board. According to the SHARC hardware reference page 23-12, SPI mode 3 is selected (clock polarity and clock phase = 1). According to the eval board schematic, a 10K Ohm pull-down resister is applied on SPI_CLK. My question is, how does SHARC prevent the booting flash (slave) from taking the first rising edge of SPI_CLK to latch input data? Because the first rising edge only means this clock pin just turning from pull-down mode to be driven by SHARC. Is there an internal mechanism that guaranties SPI_CLK is held high before SPI_FLG going low?
And, just an observation, we used the default routing for SPI booting as shown on hardware reference page 9-31. When we tried to use a pull-up to 3.3V on the SPI_CLK (DPI pin 03), we observed 2.5V.
Can someone help?