I am working on a design to take 640x480p and output it as 640x480i to the ADV7341 (using an FPGA in between to "interlace" the data). In all the of the documentation on the ADV7611 and the UG-180 I have (along with trying to just find information pertaining to this online) been unable to determine exactly when after the HSYNC and VSYNC signals are asserted, 'PIXEL1" of the frame is sent. We are not embedding the EAV/SAV codes in the datastream, we are using the discreet HSYNC and VSYNC outputs provided from the ADV7611. I am starting my design with the assumption of the point in time when VSYNC and HSYNC go low at the same time, this indicates PIXEL1 is on the datastream output. However, I realize this could be a false assumption given the fact that these have the ability to be shifted either toward or away from the actual active video. I also understand that there are a a certain number of "inactive, or black," pixels at the beginning and end of every line. This does not bother or worry me. What I need to know is where PIXEL1 occurs, how I can be sure of it, whether or not it is a true video pixel or a blank pixel at the beginning of the line.
If you can shed any light on how I might be able to determine this information, I would greatly appreciate it. In the meantime I will continue to try to dig up information at all. For the record, yet, 640x480p is the only resolution we are interested in.
Thanks so much!