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AD9279 FMC Interposer & Evaluation Board / Xilinx Reference Design

Question asked by wdrichard on May 23, 2012
Latest reply on Jun 14, 2012 by rejeesh

I notice in the reference design files that the Xilinx Virtex 6 is configured to use LVCMOS25 (2.5V) inputs while the AD9279 uses 1.8V as the supply for its serial output pins. Can someone make me feel good about this before I build my own board?


How fast can the reference design be clocked, that is, what is the maximum per channel data rate?