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ADM2587E spurious transition delays

Question asked by Evgeny on May 23, 2012
Latest reply on May 24, 2012 by Evgeny

Dear colleagues !


We use the ADM2587E for RS485 point-to-point communications at 460 kbps. The byte structure is: 1 start bit, 8 info bits, 1 stop bit. Bytes may be separated with pauses up to 1 ms long.


Sometimes bytes transferred from A-B input to RxD output appear corrupted: the first 1-to-0 input transition (i.e. the start bit beginning) has the additional delay of about 1 us at the output (additional to the normal transition delay). I mean the RxD output transition is delayed to the A-B input transition.


As a result, some bytes are shorter than the other ones. "Normal.jpg" shows the normal byte at the RxD output (1 start bit, 8 zero bits, 1 stop bit), "Problem.jpg" shows the truncated one (the same 1 start bit, 8 zero bits, 1 stop bit). Erroneous byte occurs only if the input line stays in logic one state for more than 5 us. It looks like the IC suspends and than wakes up delaying the first 1-to-0 transition.


The problem occurrence rate is from 1 per 10,000 to 1 per 10,000,000 or more (it depends on the IC sample). One bad byte per 10,000 good bytes is too much. The input voltage patterns near that transition are correct (see "Input.jpg"). The schematic diagram fragment is shown on "Sch.JPG".


Any possible workaround ? Thanks in advance.