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BF548 blackfin SPI slave problem

Question asked by asma on May 23, 2012
Latest reply on Mar 13, 2013 by Aaronwu

Hello 

BIT_CTL_MASTER

and i enable BIT_CTL_EMISO:

          chip1->ctl_reg &= (~BIT_CTL_MASTER);

         chip1->ctl_reg |= BIT_CTL_EMISO;

with this configuration, the slave can read from master correctly, but the master read a garbage from slave,

in very low spped 20khz the master can read  correctly but with 2MHZ it read it garbage.

any help please, is there other bit in the control register to be set ?

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