and i enable BIT_CTL_EMISO:
chip1->ctl_reg &= (~BIT_CTL_MASTER);
chip1->ctl_reg |= BIT_CTL_EMISO;
with this configuration, the slave can read from master correctly, but the master read a garbage from slave,
in very low spped 20khz the master can read correctly but with 2MHZ it read it garbage.
any help please, is there other bit in the control register to be set ?