We have designed and assembled two different boards with the AD8556. According to the data sheet (page 4 specifications and page 18 "shorted wire fault detection"), both inputs must be between 2 and 3V with VDD=5V. But we have VDD=3.3V because DIGIN is driven by an FPGA (we do not have logical devices under 5 V any more). In that case (VDD=3.3V), what are the thresholds VINH and VINL? I assume proportionality 1.32 and 1.98V. Is it correct?
We used the revision 0 of the data sheet. I just discovered the revision A, where it is simply stated that VDD must be between 4.5 and 5.5V. Previously it was 2.7V to 5.5V.
Thank you in advance