In our application, we are encoding 400 tiles (256x256) using 16 ADV212's. We then merge all of the tiles into one frame (5120x5120) and store the frame. When we decompress the image, we will need to pre-pend an ADI Header as well as a JP2 header to each of the tiles (tile 0 will already have a JP2 header that will need its size changed).
I'm currently architecting the decode logic. The slight problem I'm having is that, the JP2 header is 187 bytes (using the current settings). It would make things easier if we could have the data aligned to a 64-bit boundary. That way, data from DDR could be read into a FIFO and input directly to the ADV212.
To that end, could we pad the input to the ADV212 by 5 bytes? That is, send 5 bytes of zeros to the ADV212 before the ADI header? I see that we could include other JP2 markers into the JP2 header, but I"m not sure that would help.