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AD9788 Synchronization

Question asked by des@DRS on May 17, 2012
Latest reply on Sep 12, 2012 by Tguy

I cannot see SYNC_O pulses on AD9788 (pins 62,63) . Please review if my set up is correct. When does the Master send SYNC_O pulses- all the time or just when the DDS is updated?


I have multiple AD9788 in Master/Slave config;  SYNC_O from the Master is echoed back to itself and Slave devices by an LVDS fan-out buffer. I am using PN code sync, so I set reg03 (Multi-Sync Contrl) of the Master to 0x8600 0400; for the Slave, reg03 =0x8400 0400. The DCTL reg 01 in both Master & Slave =0x3380; PN Code Sync Enabled, Sync Mode ON; Interp =4.


All devices have a 900M clock at the REF CLK input -pins 5&6; the input IQ data rate is 225MHz. The internal DDS is 230M+/-5MHz.


The alternative to PN Mode Sync is Pulse sync to a System Clock applied tothe TXENBLE pin. I do not have a system clock, or a need to sync to one; I need phase consistency for beam forming so I chose the PN Sync Mode.