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pci initialization with bf535

Question asked by novemer on May 14, 2012
Latest reply on May 29, 2012 by jobo23

hi all:

  i use bf535 pci interface with device mode.i've already initialed pci part with exemple ee-207.but the pc os can not recognize the device,and the bios can not pass the BIT test.

  another question is about the pll module.the divided clock is seem be locked.the sclk is 20x in the design.but actually it is not.1x or 2x maybe.

 

here is the code:

initial pci:

*pPCI_STAT = *pPCI_STAT; 
*pPCI_CTL = 0;    //pci controller reg
*pPCI_ICTL = 0;    //pci interrupt controller reg
__builtin_bfin_ssync();

*pPCI_CFG_VIC = PCI_VID;
*pPCI_CFG_DIC = PCI_PID;

*pPCI_CFG_CMD = 0x4;  //pci configuration command reg
*pPCI_CFG_RID = 0x1;

*pPCI_CFG_CC = (0x11 << 16) | 0x00; //pci configuration classcode

*pPCI_CFG_CLS = 0;     //cache line size
*pPCI_CFG_MLT = 0;
*pPCI_CFG_HT = 0;
*pPCI_CFG_SVID = PCI_VID;
*pPCI_CFG_SID = PCI_PID;
*pPCI_CFG_IP = 0x1;
*pPCI_CFG_IL = 0;
*pPCI_CFG_MING = 0x1;
*pPCI_CFG_MAXL = 0x2;

*pPCI_DMBARM = PCI_MEM_BARMASK;   //device mem bar mask
*pPCI_DIBARM = PCI_IO_BARMASK;   //device io bar mask
*pPCI_TMBAP = (void *)PCI_MEM_TPTR;  //inbound mem base adress reg
*pPCI_TIBAP = (void *)PCI_IO_TPTR;  //inbound io base adress reg

*pPCI_ICTL = PCI_ICTL_RESET;

*pPCI_CTL = PCI_CTL_ENABPCI | PCI_CTL_FASTBCK2BCK | PCI_CTL_ENABINTA;
__builtin_bfin_ssync();

 

initial pll:

*pSIC_IWR = 0x100000;  //system interrupt wakeup-enable reg
__builtin_bfin_ssync();

*pWDOG_CNT = 0x20;   //watchdog count reg
__builtin_bfin_ssync(); 

*pPLL_CTL = 0x6901;    //bypass
*pPLL_CTL = 0x6801;   //pll 20x non-bypass
__builtin_bfin_ssync();

*pWDOG_STAT = 0;   //watchdog status reg
__builtin_bfin_ssync();

*pWDOG_CTL = ENABLE_GPI; //watchdog control reg
__builtin_bfin_ssync();


asm("CLI R7;");
asm("IDLE;");
__builtin_bfin_ssync();
asm("STI R7;");

*pWDOG_CTL = 0x8006;
__builtin_bfin_ssync();

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