How can I configure PPI on BF815 for this LCD - TX09D70VM1CDA by Hitachi? Oscillogram on pages 8-2/6 and 8-3/6 see signals HSYNC and DTMG.
I think the periods of HSYNC and DTMG are equal. From the Interface timing and the symbol definitions given in Table 8.1 in the datasheet, HSYNC period=T6(273 CLKs). and DTMG period=T11+T10(273 CLKs). HSYNC can be generated using PPI_FS1 with PULSE_HI=0 and WIDTH=T7, PERIOD=T6. After this timer is enabled, there can be approximately around 22 CLKs(T6 minus T8) before DTMG goes high. So, this can be generated using another timer with WIDTH=T11 and period same as HSYNC but PULSE_HI=1(This Timer can run on an SCLK configured same as PPI_CLK). There will be valid data as long as this DTMG is high(240 CLKs).
I would suggest you to have a look at the application note EE-256 and the associated code.
Also, the following code in the VDSP directory can be helpful which has an example for BF518.
$\VisualDSP 5.0\Blackfin\Examples\Landscape LCD EZ-EXTENDER\LCD_ColorBarDisplay
According to the LCD datasheet, it looks like the DTMG signal is the data valid signal which has to be appropriately generated to avoid frame sync problems.
Thanks and Regards,
Thanks for the answer, I examined EE-256 and code example, but how i can get delay between fallen edges of HSYNC and DTMG equal five data clocks?
#define H_PERIOD 273
#define H_PULSE 5
#define V_PULSE 33
#define V_PERIOD 273
unsigned short data;
void main( void )
TimerInit(pTIMER5_CONFIG, PWM_OUT|PERIOD_CNT, 18, 9); //DotClock
TimerInit(pTIMER0_CONFIG, PWM_OUT|PERIOD_CNT|TIN_SEL|CLK_SEL|EMU_RUN, H_PERIOD, H_PULSE);
TimerInit(pTIMER1_CONFIG, PWM_OUT|PERIOD_CNT|TIN_SEL|CLK_SEL|EMU_RUN, V_PERIOD, V_PULSE);
*pPPI_DELAY = 0;
*pPPI_COUNT = 239;
*pPPI_FRAME = 320;
*pPPI_CONTROL = PORT_DIR|PPI_TX_MODE|PPI_XFER_TYPE_11|PPI_PORT_CFG_01|DLEN_16;
*pDMA0_START_ADDR = &data;
*pDMA0_X_COUNT = 240;
*pDMA0_X_MODIFY = 2;
*pDMA0_Y_COUNT = 320;
*pDMA0_Y_MODIFY = 2;
*pDMA0_PERIPHERAL_MAP = 0x0;
*pDMA0_CONFIG = WDSIZE_16|DI_EN|0x1000|DMA2D;//|SYNC
*pDMA0_CONFIG |= DI_EN;
*pDMA0_CONFIG |= DMAEN;
*pPPI_CONTROL |= PORT_EN;
*pTIMER_ENABLE = TIMEN5|;
*pTIMER_ENABLE = TIMEN1;
*pTIMER_ENABLE = TIMEN0;
I am referring to the LCD datasheet you had attached in your earlier post. According to the waveforms there, the clocks between falling edge of HSYNC and DTMG assertion is T6-T1(which i think is >5 CLKs). HSYNC and VSYNC signals can be generated by configuring Timers 0 and 1. DTMG signal can also be generated using a GP Timer whose PERIOD= T11 and WIDTH=T10(with PULSE_HI=1).
This display does not have an external signal VSYNC. It is controlled only by HSYNC and DTMG. Periods of these signals are not equal, so they are out of sync. Whether there is an offset to synchronize them?
I'm trying to trace how the image 57.
in fact - image 58.
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