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HSC-ADC-EVALCZ

Question asked by adi_susan Employee on May 10, 2012
Latest reply on May 10, 2012 by TonyM

We plan to use HSC-ADC-EVALCZ (Xilinx Virtex-4 FPGA-based buffer memory board 
Used for capturing digital data from high speed ADC)  for interfacing the AD9467 eval board. 

 

There is some point that I want to clarify for HSC-ADC-EVALCZ :

  1. Is it possible to interface digital signal to HSC-ADC-EVALCZ using P1,P2,P3 other than DSP board as mentioned in application notes  ? I want to interface anoth SPI ADC and DAC using P1,P2 and P3 on HSC-ADC-EVALCZ. 
  2. What is the voltage level of +VADJ in HSC-ADC-EVALCZ  ?As per given formula in ADP3334 datasheet and voltage specified for U20 in HSC-ADC-EVALCZ  is not matching.I am attaching my calculation.

                          

VFB

VOUT

Specified in DatasheetHSC-ADC-EVALC

R1

R2

  1. 1.178
  2. 1.736
  3. 1.800

107

226

  1. 1.178
  2. 3.377
  3. 3.300

140

75

  1. 1.178
  2. 1.92
  3. 2.50

107

169

 

       3. Can we change it to 3.3 VDC as present design it is 2.5 VDC ?

 

        4.There is no SRAM and FLSH mounteed on HSC-ADC-EVALCZ  board. Can we get the HSC-ADC-EVALCZ  with  FLASH and SRAM ?

Looking forward to your feedback and thanks for your great help!

 

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