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AD9548 - SYSCLK Connectivity

Question asked by Fred1 on May 10, 2012
Latest reply on May 10, 2012 by pkern



I am referring to the current datasheet of the AD9548 and EV-Board.


I intend to use an 10MHz OCXO with 3.3V CMOS output to drive the SYSCLK input of the PLL. There is a voltage divider required to bring the voltage down to 1.8V That is clear so far.


However, the datasheet not clear when it comes to AC coupling:


Datasheet Page 37:

When interfacing the TCXO/OCXO, a voltage divider on the output should be used to reduce the voltage swing to 1 V p-p, and that signal should be ac-coupled to the SYSCLKP pin. The SYSCLKN pin can be bypassed to ground with a 0.01 μF capacitor.


Datasheet Page 6:

SYSCLK ...can accommodate single-ended input by ac grounding unused input. (nothing mentioned about the used pin)


Evaluation Board Ref. E:

The EV Board has no capacitor between OCXO (Y2) output divider and SYSCLKN. There is also no capacitor from the unused SYSCLKP pin to ground which could be loaded if the on-board OCXO is used.



Question: Is there a capacitor between OCXO output voltage divider and SYSCLKP required or is it sufficient if only SYSCLKN is grounded via 10nF?