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Clock signals for AD1974

Question asked by Chrill on May 10, 2012
Latest reply on Jun 20, 2012 by digital



I have two questions concerning the AD1974s clock signals:


1. From the datasheet it seems to me that I can run the AD1974 solely on the ALRCLK, i.e. the ALRCLK is externally provided (LRCLK in slave mode), PLL input is set to ALRCLK, ADC clock source select is set to PLL clock (generating the master clock), BCLK is set to master and BCLK source is set to 'Internally generated'.

This means that I won't need to connect a crystal and I don't need to provide a BCLK. Can someone confirm this?


2. Serial data can be transmitted without an explicit BCLK. This sounds like a neat way to reduce EMI, however, does this imply that I need to generate a BCLK from LRCLK (using a software PLL?) on the host side to be able to read data on the serial port? Or do I miss something here?

(EDIT: btw, in my application I'm using an external word clock generator, so LRCLK is not provided by the host controller)


Any comments are appreciated!