Per the device ADV7341 video encoder:
I wish to clock data to the device in mode “010” DDR + EAV/SAV enabled (data is 8-bit wide).
Desired standard is 1080i (SMPTE 274M), 30FpS.
The 274 standard and its related 861 standard, specify that active video spans over 1920 clocks.
Assuming 4:2:2 color sampling and 8-bit interface, the 1920 x 2 = 3840 bytes can be clocked to the device within
just 1920 clocks, when data is clocked twice per clock, hence the DDR interface.
However, in Figure 133 of datasheet, EAV and SAV codes are data which are clocked only once per clock. The Figure perhaps suggests that the device switches automatically from SDR (while in horizontal blank) to DDR (while in active vide region).
The problem is:
1. This alleged switching from SDR to DDR is not clearly specified in the datasheet, if, this alleged switching exists at all.
2. Figure 9 shows clearly that the EAV/SAV are also clocked in the device in DDR mode, hence only 2 clocks are needed for an EAV or SAV of 4 bytes.
But, Figure 133 contradicts this by specifying 4 clocks (“4T”) for and EAV or SAV.
I think the only way to make sense of the diagrams, is to assume that although it is not specified, the device always works in DDR mode, but, during horizontal blanking, each byte is duplicated. This makes Figure 9 (which shows that EAV/SAV change every half-clock) wrong.
Is my assumption correct ?
If not, how do I clock data into the device in 1080i with DDR interface (data width = 1 byte). ?
Thanks in advacne, would appreciate your cooperation.