i have two question
1. what is the different between ADV7611 Final Silicon and ADV7612 Final Silicon
RD_INFO[15:0], IO, Address 0xEA[7:0]; Address 0xEB[7:0]
0x2041 ADV7611 Final Silicon
0x2051 ADV7612 Final Silicon
2. the LLC pixel clock is not stable when ADV7612 hdmirx in ttltx out function in YCbCr 36bits mode.
our board description:
we are use ADI ADV7612 chip, the board is layout by ourself.
28.63636 MHz clock from clock generate is connect to XTALP, XTALN is left to unconnect
we use our self usb to i2c cable to read/write ADV7612. the cable is check in other project and stable.
our detail step:
1. connect hdmitx to ADV7612 port A, open the hdmitx to transmiter 720x480p@60 video color bar data.
(our hdmitx not care HPD, and EDID, will directly send video data use TMDS channel)
2. power on ADV712 board.
3. push reset button to reset ADV7612
4. configure other 7 i2c slave address following recommend setting
98 F4 80 ; CEC
98 F5 7C ; INFOFRAME
98 F8 4C ; DPLL
98 F9 64 ; KSV
98 FA 6C ; EDID
98 FB 68 ; HDMI
98 FD 44 ; CP
5. check and dump the default value.(default+addr_cfg.txt)
5.1 the default value is right and can read/write
80 ; CEC
4C ; DPLL
68 ; HDMI
44 ; CP
5.2 the read back default value is not right but not all zero
7C ; INFOFRAME
5.3 the read back default value is zero, and can not write.
64 ; KSV
6C ; EDID
6. load ADI item "6-1d1" in ADV7612-VER.2.9c.txt
7. dump the configure after_load.txt
8. check the ttltx output from ADV7612
the LLC pad clock is about 13.5Mhz but not stable.
video data pad: some pad has toggle
sometimes TMDS clock is detected on port A read back from register(TMDS_CLK_A_RAW, IO, Address 0x6A )
TMDS clock is always not lock TMDSPLL_LCK_A_RAW, IO, Address 0x6A
our dump files
1. default value after reset and configure 7 i2c address: default+addr_cfg.txt
2. load file item 6-1d1 and configure the crystal select register: 6-1d1.txt
3. dump file after load confiuger: after_load.txt