My Blackfin really likes running with data cache enabled (it's quite fast). However, when I enable data cache, the asynch flash memory stops functioning fully. Specifically, after writing the special sequence to erase a block, I'm not able to force Read cycles through the cache and onto the external memory buses.
I need my SDRAM to be cacheable, but none of the async memory should be cacheable. My system has:
- 1MB flash on async memory bank 0 (@ 0x20000000)
- 1MB allocated to another peripheral on async memory bank 3 (@ 0x20300000 )
- 32MB SDRAM (@ 0x00000000)
If I halt at runtime, DMEM_CONTROL = 0x0000 100F, which means DCPLBs are enabled. I also have an entry in my DCPLB table
DCPLB_ADDR = 20300000
DCPLB_DATA = 0002001D
According to this, I would expect that the async memory bank 3 should not be cacheable, as the flag CPLB_L1_CHBL bit 12 = 0 . However, at run time, I can tell that cache is being used because my data will update the first time and then stop updating, except a few 64-byte chunks here and there. If I disable data cache, everything is stable again. I am using MDMA to transfer data from async bank 3 to SDRAM, so I'm not sure if that's involved. I see there is a silicon anomaly, but I am not using descriptors for MDMA so I don't think that's the problem.