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problem about using SYNC CLK port(AD9910 & FPGA)

Question asked by shawn.J on May 6, 2012
Latest reply on May 7, 2012 by DSB



I configure a module of frequency generation with high speed switching time(500ns).

For charateristic of high speed switching time  I will use FPGA(lattice,MACHxo series) & AD9910.


DDS' REF CLK is 1GHz and then  FPGA' ref CLK is 250MHz using DDS's SYNC CLK port.

For operating FPGA, FPGA's clk must be setting.

But  at the moment of FPGA & DDS are powered on, DDS's SYNC CLK port is not working.

So FPGA is not working too. 


I'm wondering to know how to using SYNC CLK port without any CFR at the moment of FPGA & DDS are powered on.

Is it possible??