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default polarity of SDP synchronization output signals

Question asked by on May 4, 2012
Latest reply on May 4, 2012 by mattp

Hello experts,


I am reading 7850's user guide, and could anyone clarify what is the default polarity? It means active high or active low?


sdp_fld_pol, Addr 94 (sdp_IO), Address 0xB1[2]

A control to change polarity of FIELD/DE


sdp_fld_pol Description

0 Inverted FIELD/DE pin polarity

1 << Default FIELD/DE pin polarity


Similar to this register, sdp_hs_pol, sdp_de_pol, and sdp_vs_pol use the same term.


The second question is: when CVBS as input, will the polarity of de/vsync/hsync of HDMI Tx be decided by the three registers? If not, how they are decided?


Thank you in advance.