I am trying to configure AD9910 to do a frequency ramp upwise and later a downwise one. I manage this by connection DROVER to DRCTL and it seems to work fine.
However, I can only get it to the both ramps when the timestep is greater than 0b...1000 (i.e. 8 steps of CLK) instead of being able to run at steps of just 0b...001 (i.e., 1 step of CLK). This results in poor phase noise.