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impact on filter coeficient / auto switching 44.1-48 and MCLK

Question asked by maxidcx on May 2, 2012
Latest reply on May 2, 2012 by BrettG

Hello,

 

I couldnt find a conversation on this so here is the problem : how to configure sampling frequency in sigmastudio and what is impact on the filter coeficient when I2S input rate is changing ? what is internal DSP jitter and is it worth using a second ASRC output to reduce DSP internal jitter?

 

here is more context:

 

We are designing a dsp board with ADAU1445 and the I2S input is coming from an SPDIF receiver .

The master clock will come from 2 VCXO and a microcontroler will switch between 24.576 or 22.579 depending if the source is playing 44.1/88.2/176.4 or 48/96/192 (by monitoring the SPDIF receiver frequency calculator)

 

we plan to pass trough a first ASRC to always force 2x upsamplig or :2 down sampling depending on the input rate, in order to always work in the domain 88.2 or 96khz, while the master clock provided by the selected VCXO will always be equal to 256fs.

 

The DSP will drive external DAC (I2S) and the same master clock will be used for the DAC.

the complete solution is expected to deliver high end audio experience.

 

0) Shall I devlop the sigmastudio project based on 96KHZ FS ? or do I need 2 separate projects one for 96 then one for 88.2 (but then I dont find 88.2 in the FS drop down!!!)

 

1) what is the right configuration for the PLL pins.

 

2) whats happen with the filters response when the sample rate is 88.2 (with master clock reduced to 22.579) ? I guess the filter will keep the same frequency response as the mclock is kept to 256fs , right ? otherwise I have to dynamically update the coefficient !??

 

3) can I rely on the ASRC to auto lock and always provide the 1x/ 2x or 0.5x itself without changing the registers myself so the rate is always 96 or 88.2 ?

 

4) what THD can I expect from going trough this first ASRC for this optional upsampling/downsampling ? would do you recomend another approach using a FIR filter as the frequency will always be a multiple (1, 2 or 0.5)

 

5) what will be the jitter produced by the DSP in master mode as seen by the DAC (slave) in this configuration ?

 

6) to reduce this jitter, is their any benefit to use the second ASRC to reclock the output  of the dsp with the VCXO master clock... ?

 

7) if no, it it worth reclocking the LRCLK and BCLK with some FlipFlop synchronized on the master clock ?

 

8) if yes, what is the recomendation for configuring this second ASRC and the clock signals and the ASRC mode Salve/Master to the slave DAC?

 

Many thanks in advance

cheers and long life to sigmadsp !

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