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Questions on details of DMA on the ADSP 21489

Question asked by TABWE on Apr 30, 2012
Latest reply on Dec 31, 2014 by KRZ

Dear all,

 

I'm trying to understand (chained) DMA data handling between SPORTs and the internal memory on a ADSP 21489 (EZ-Kit) using the Talkthrough_IIR_Accelerator included with Visual DSP.

 

While the general concept of chained DMA and the way it is used in this example is more or less clear, I would be happy if somebody would be as kind as to confirm some points and to give some more detailed information than the HRM does.

 

1) To confirm:

Internal Memory Index (II):

The starting target adress in the internal memory, to which data (Payload from the SPORTS) is transferred

 

Index Modifier Register (IM):

The increment which is added to the target address after a DMA write (which equals the transfer of one word/sample?)

 

Word Count (IC):

The number of words/samples to transfer per DMA Sequence (which is one TCB Block Execution?)

 

Chain Pointer (CP):

Points to the next TCB Block executed on the DMA Channel.  (See Question below!)


What exactly is a DMA Channel?

In my understanding, a DMA channel a facility which is assigned to a e.g. a serial port being able to perform data transfer described by the four above-mentioned registers / or TCB?

 

On TCBs:

In my understanding, the IOP fetches the rest of the TCB from the internal memory after an address was supplied via the CP register. Where does the IOP put the TCBs?


2) Questions

Principle of DMA chaining

According to the InitSPORT function in the init_sport.c, the relevant lines for DMA chaining look something like (also see attached file)

 

TCB_Block0_IN[0] = (int)TCB_Block1_IN + 3;

// Chain Pointer TCB0 = Adress of Internal Memory Index in TCB 1

// DMA Chaining

 

I'm wondering why the TCB_Block0_IN element holding the Chain Pointer of the ongoing transfer holds the last address word of the TCB_Block1_In array (which is the element of the array containing the internal memory index of the next DMA sequence) rather than the adress of the very first element TCB_Block1_IN[0]?

 

DMA Startup

What is the idea of these lines? I understand that these lines fill the Chain Pointer Registers of the DMA channel for the first time and thus initiate the chained DMA transfer.

 

However, I again don't understand why TCB_BLOCK0_In + 3 is mapped into the CP rather than TCB_Block0_In?

Also, I don't understand the use of & 0x7FFFF | (1<<19).

 

The HRM says that 0x7FFFF masks the adress (which unfortunately isn't explained in any detail) and that 1<<19 is used to set the PCI bit.


// Trigger first DMA Sequence on Input DMA channel  (SPORT1, Channel A)

*pCPSP1A = ((int) TCB_Block0_IN + 3) & 0x7FFFF | (1<<19);

 

Moreover, I'm wondering why this is only done during startup and not for the TCB Blocks set by

 

TCB_Block0_IN[0] = (int)TCB_Block1_IN + 3;


Struchture of the Serial Port Chain Pointer Registers

From the HRM, I understand that the CPSPx registers are structured as follows:

     Bits 18 - 0:  IIx address Next chain pointer address

     Bit 19:19     PCI Program controlled interrupt

                0 = no interrupt after current TCB

                1 = interrupt after current TCB

     Bits 27 - 20: IIx address Next chain pointer (external address)

 

What is the use of the two adress fields? Are bits 27-20 only used if I want to transfer data to the external memory? If so, what is the value of these bits if data is transferred to internal memory? How long are the adress words used in external / internal memory?

 

I've attached the complete init_sport.c which I have commented completely as far as I've understood.

 

Unfortunately, neither the HRM as well as most articles on EZ (especially http://ez.analog.com/thread/1453) couldn't provide much more clarity in the above mentioned question.

 

I'd appreciate every help in understanding these details on DMA.

 

Thanks!

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