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fpga and dsp

Question asked by bansal on Apr 27, 2012
Latest reply on May 8, 2012 by Mitesh

hi

in my custom borad design i have connected  DSP to FPGA by using flag2 and flag3 mean MS2 and MS3 signal..so i can use fpga as a memory,

when i am writing in fpga through dsp , there i got a problem .

i am not getting to understand the signal level of address line.

i am writing at address 0x0C000001 (that is bank 3 address) , but in fpga wen i check pin dsp_add(0-23) , there i m not getting same address as where i m writing ..

can any one tell how this address mapping is happening in AMI mode ..and how many write and read cycle (sdclk timing ) it will take for AMI mode ?

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