How can I use PCG to generate SCLK and LRCLK for I2S mode ?
As per the I2S mode, LRCLK should be driven at the falling edge of SCLK. In other words, LRCLK edge should coincide with the falling edge of the SCLK. To satisfy this requirement, the phase of the frame sync should be programmed accordingly in the PCG_CTLxx registers.
Assume that the input clock source for both clock and frame sync is same and both CLK and FS are enabled at the same time. Also assume that the divisor value needed to generate the required SCLK is CLKDIV=4. Then, for 32 bit word length, divisor value for LRCLK should be FSDIV = 64*CLKDIV = 256.
By default, for phase= 0, rising edge of both SCLK and LRCLK will coincide. To make sure that LRCLK edges conincie with the falling edge of the SCLK, phase value that needs to be programmed is CLKDIV/2 = 2. It can be done by following instructions:
ustat1=CLKDIV|((CLKDIV/2)<<20); dm(PCG_CTLx1) = ustat1;
For details on how to program phase of the frame sync using PCG_CTLxx registers, please refer the corresponding Hardware Reference Manual.
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